Publication in the Diário da República: Aviso n.º 3961/2023 - 29/03/2023
5 ECTS; 1º Ano, 1º Semestre, 60,0 TP , Cód. 62633.
Lecturer
- Manuel Fernando Martins de Barros (1)
(1) Docente Responsável
(2) Docente que lecciona
Prerequisites
N.A.
Objectives
Understand and apply the most fundamental techniques and concepts used in the study of Digital Logic Systems. Develop low- and medium-complexity projects for combinational and sequential logic circuits. Utilize low- and medium-scale integration digital integrated circuits. Introduction to CAD tools and hardware description languages.
Program
1. **Number Systems:** Base 10, base 2, base 8, and base 16; conversion between number bases; performing arithmetic operations in different bases; weighted and non-weighted binary codesnatural binary, BCD, 2's complement, Gray code, 7-segment code, ASCII.
2. **Combinational Logic Circuits:** Representation of logic functions; logic operators (logic gates); truth tables, symbols, and logic diagrams; laws, theorems, and postulates of Boolean Algebra; simplification of combinational logic functions using Boolean Algebra and Karnaugh maps; design and implementation of combinational logic circuits.
3. **Medium-Complexity Combinational Circuits:** Multiplexers; demultiplexers and decoders; logic comparators; arithmetic circuits; A/D converters; encoders.
4. **Digital Circuit Technology and Logic Families:** TTL and CMOS logic families; propagation delay, operating speed, and figure of merit; fan-out and fan-in; totem-pole, open-collector, and tri-state outputs; interfacing between TTL and CMOS logic families; fault detection and troubleshooting in digital circuits.
5. **Sequential Circuits:** Asynchronous ("latch") and synchronous ("flip-flop") memory cells; D, T, and J-K flip-flops; timing diagrams; state machines; analysis and synthesis of synchronous sequential circuits; state excitation and transition tables, state diagrams, and self-correction.
6. **Registers and Counters:** Shift registers; inter-register operations; ring counters and modulo-2N counters; BCD counter.
7. **Introduction to CAD tools and hardware description languages:** Study of the VHDL language with the use of VHDPlus tools.
Evaluation Methodology
Regular attendance and active participation in class are considered a fundamental element for success in this course.
Evaluation Components:
Tests or Final Exam (50%): A minimum grade of 8 out of 20 is required.
Group or Laboratory Assignments (50%): A minimum grade of 10 out of 20 is required.
Bibliography
- Barros, M. (0). Sebenta de Sistemas Digitais. Acedido em 15 de outubro de 2019 em https://doctrino.ipt.pt/course/view.php?id=3971
- Dias, M. (2010). Sistemas Digitais - Princípios e Prática. (Vol. 1). Lisboa: FCA
- Nunes, F. (0). Sistemas Lógicos - CTeSP-AI (apresentações das aulas, exercícios e guias de laboratório). Acedido em 20 de outubro de 2020 em https://doctrino.ipt.pt/course/view.php?id=3971
Teaching Method
Theoretical-practical classes for the explanation of theoretical material and the solving of exercises. Laboratory classes for the completion of practical lab assignments.
Software used in class
**Free Tools:**
* Logisim ([http://www.cburch.com/logisim](http://www.cburch.com/logisim))
* Simulador digital 095 (Digital Simulator 095)
* VHDPlus ([https://vhdplus.com](https://vhdplus.com))
* Eagle ([http://www.cadsoftusa.com](http://www.cadsoftusa.com))
* LTSpice ([http://www.linear.com/designtools/software/](http://www.linear.com/designtools/software/))
**Other Tools Students Can Explore (Commercial):**
* MultiSim ([http://www.ni.com/multisim/pt/](http://www.ni.com/multisim/pt/))
* Proteus ([http://www.labcenter.com/](http://www.labcenter.com/))
