Publication in the Diário da República: Aviso n.º 11062/2017 - 25/09/2017 + Decl. Rectif. nº 359/2018 de 11 de Maio
5 ECTS; 1º Ano, 1º Semestre, 67,50 TP , Cód. 62736.
Lecturer
- Francisco José Alexandre Nunes (1)(2)
(1) Docente Responsável
(2) Docente que lecciona
Prerequisites
Not applicable
Objectives
To understand and utilize the most commonly used fundamental techniques and concepts in the study of Digital Logic Systems. To develop low and medium-complexity combinational and sequential logic circuit designs. To use low and medium-scale digital integrated circuits.
Program
1. Numbering systems: base 10, base 2, base 8, and base 16; conversion between numbering bases; performing arithmetic operations in different bases; weighted and unweighted binary codes - natural binary, BCD, two's complement, Gray code, 7-segment code, ASCII.
2. Combinational logic circuits: representation of logical functions; logical operators (logic gates); truth tables, symbology, and logic diagrams; laws, theorems, and postulates of Boolean algebra; simplification of combinational logic functions through Boolean algebra and Karnaugh maps; design and implementation of combinational logic circuits.
3. Medium-complexity combinational circuits: multiplexers; demultiplexers and decoders; logic comparators; arithmetic circuits; A/D converters; encoders. 4. Digital circuit technology and logic families: TTL and CMOS logic families; propagation time, operating speed, and merit factor; fan-out and fan-in; totem-pole, open-collector, and tri-state outputs; interface between TTL and CMOS logic families; fault detection and error finding in digital circuits.
5. Sequential circuits: asynchronous ("latch") and synchronous ("flip-flop") memory cells; D, T, and J-K type flip-flops; timing diagrams; state machines; analysis and synthesis of synchronous sequential circuits; excitation and state transition tables, state diagrams, and self-correction.
6. Registers and counters: shift registers; operations between registers; ring counters and module 2N counters; BCD counter.
Evaluation Methodology
Final Grade: NF = CT*60% + CP*40%
(min. 10 points)
Theoretical Component: CT - tests or final exam
(min. 9 points)
Practical Component: CP - practical laboratory work
(min. 10 points)
Bibliography
- Barros, M. (0). Sebenta de Sistemas Digitais. Acedido em 21 de fevereiro de 2026 em https://politecnicotomar.sharepoint.com/:f:/r/teams/SistemasLgicos202526/Material%20de%20Aula/Outros%20textos%20de%20apoio?csf=1&web=1&e=ITbbmd
- Dias, M. (2010). Sistemas Digitais - Princípios e prática. (Vol. 1). Lisboa: FCA
- Khormaee, I. (2012). Digital Logic Design. Acedido em 21 de fevereiro de 2026 em https://politecnicotomar.sharepoint.com/:f:/r/teams/SistemasLgicos202526/Material%20de%20Aula/Outros%20textos%20de%20apoio?csf=1&web=1&e=OHEQpk
- Nunes, F. (0). Sistemas Lógicos CTeSP-IEMI (apresentações das aulas, exercícios e guias de laboratório). Acedido em 21 de fevereiro de 2026 em https://politecnicotomar.sharepoint.com/:f:/r/teams/SistemasLgicos202526/Material%20de%20Aula/Apresenta%C3%A7%C3%B5es%20das%20aulas?csf=1&web=1&e=ituXpL
Teaching Method
Theoretical and practical classes for presenting theoretical material and solving exercises. Laboratory classes for carrying out practical laboratory work.
Software used in class
Logisim evolution
